Low Power Gbit/sec Low Voltage Differential Signaling I/O System
نویسنده
چکیده
The effects that I/O circuits have on the overall system performance are becoming more and more pronounced nowadays, as many digital processors reached GHz frequency range while I/O operates only up to MHz range. Extensive studies have been done on I/O signal processing and multi-clocking schemes to increase number of bits per Hz of transmission. In this paper, a circuit level approach to this problem is presented, in particular a low voltage differential signaling (LVDS) interface circuitry is investigated. Simulations have shown 3.0Gbit/sec transmission rate is achieved in a 0.18μm technology while transmitter and receiver dissipate less than 20mW and 25mW power respectively.
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تاریخ انتشار 2002